FAILURE MECHANISM BASED STRESS TEST QUALIFICATION FOR INTEGRATED CIRCUITS
(1) Preconditioning, JEDEC J-STD-020
Bake:125℃、24H
Temp/Humidty:85℃60%、168H
Reflow:260℃MAX、3times
77pcs./1Lot Total 3Lots(231pcs).
Price: xxxxx jpy yen
(a) It does not include shipping charges.
(b) It does not include the electrical characteristics measurement cost
(2) Autoclave, JESD22-A101
85C/85%/1000H
Autoclave:77pcs./1Lot Total 3Lots(231pcs).
Temperature Cycling :77pcs./1Lot Total 3Lots(231pcs).
Price:xxxxxx jpy yen
(a)It does not include shipping charges.
(b)It does not include the electrical characteristics measurement cost
(3) Temperature Cycling, JESD22-A104
105C(30min) <-> 50C(30min), 1000cys
77pcs./1Lot Total 3Lots(231pcs).
Price:xxxxxxx jpy yen
(a) It does not include shipping charges.
(b) It does not include the electrical characteristics measurement cost
(4) High Temperature Storage Life, JESD22-A103
150C/1000H
45pcs./1Lot Total 1Lots(45pcs).
Price:xxxxxxx jpy yen
(a) It does not include shipping charges.
(b) It does not include the electrical characteristics measurement cost
(5) Temperature-Humidity-Bias, High Temperature Operating Life, Power
Temperature Cycle
These test is a test for applying a voltage .
Burn-in board is required .
Information of the signal to be applied to the device is required .